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1 ? isl6540a data sheet may 29, 2007 fn6288.3 single-phase buck pwm controller with integrated high speed mosfet driver and pre-biased load capability the isl6540a is an improved version of the isl6540 single-phase voltage-mode pwm controller with input voltage feedforward compensation to mainta in a constant loop gain for optimal transient resp onse, especially for applications with a wide input voltage range. its integrated high speed synchronous rectified mosfet drivers and other sophisticated features provide complete cont rol and protection for a dc/dc converter with minimum external components, resulting in minimum cost and less engineering design efforts. the output voltage of the conver ter can be precisely regulated with an internal reference voltage of 0.591v, and has an improved system tolerance of 0.68% over commercial temperature and line load variations. an external voltage can be used in place of the internal reference for voltage tracking/ddr applications. the isl6540a has an internal linear regulator or external linear regulator drive options for applications with only a single supply rail. the internal oscillator is adjustable from 250khz to 2mhz. the integrated voltage margin ing, programmable pre-biased soft-start, differential remote sensing amplifier, and programmable input voltage por features enhance the isl6540a value. pinout isl6540a (28 ld 5x5 qfn) top view features ? vin and power rail operation from +3.3v to +20v ? fast transient response - 0 to 100% duty cycle - 15mhz bandwidth error amplifier with 6v/ s slew rate - voltage-mode pwm leading and trailing-edge modulation control - input voltage feedforward compensation ? 2.9v to 5.5v high speed 2a/4a mosfet gate drivers - tri-state for power stage shutdown ? internal linear regulator (lr) - 5.5v bias from vin ? external lr drive for op timal thermal performance ? voltage margining with independently adjustable upper and lower settings for system stress testing and over clocking ? reference voltage i/o for ddr/tracking applications ? improved 0.591v internal reference with buffered output - 0.68%/1.0% over commercial/industrial range ? source and sink overcurrent protections - low-and high-side mosfet r ds(on) sensing ? overvoltage and undervoltage protections ? small converter size - qfn package ? oscillator programmable from 250khz to 2mhz ? differential remote voltage sensing with unity gain ? programmable soft-start with pre-biased load capability ? power good indication with programmable delay ? en input with voltage monitoring capability ? pb-free plus anneal available (rohs compliant) applications ? power supply for some microprocessors and gpus ? wide and narrow input voltage range buck regulators ? point of load applications ? low-voltage and high current distributed power supplies vsen+ refout marctrl pg en vmon comp fs phase boot ugate fb pgnd pg_dly vcc vsen- lgate gnd ss ofs- lsoc hsoc pvcc lindrv vff vin ofs+ refin 1 2 3 4 5 6 7 21 20 19 18 17 16 15 28 27 26 25 24 23 22 8 9 10 11 12 13 14 gnd bottom side pad ordering information part number* (note) part marking temp. range (c) package (pb-free) pkg. dwg. # isl6540acrz isl6540 acrz 0 to +70 28 ld 5x5 qfn l28.5x5 isl6540acrza isl6540 acrz 0 to +70 28 ld 5x5 qfn l28.5x5 isl6540airz isl6540 airz -40 to +85 28 ld 5x5 qfn l28.5x5 isl6540airza isl6540 airz -40 to +85 28 ld 5x5 qfn l28.5x5 *add ?-t? suffix for tape and reel. note: intersil pb-free plus anneal products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2006, 2007. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn6288.3 may 29, 2007 block diagram vcc 1.8v boot ugate gnd phase en ofs+ ofs- fb power-on reset (por) comp mar_ctrl refin pgnd lgate source ea pwm pvcc lsoc vcc gate control logic internal series fs voltage reference refout 100 a ss pg_dly pg pgood comp vmon vin linear hsoc 100 a ov/uv comp g = -1 sinking ocp source ocp vsen+ vsen- lin_drv external series linear driver vff oscillator soft-start and fault logic ocp ota g = 1 unity gain diff amp comp v ref = 0.591 v margining gnd isl6540a
3 fn6288.3 may 29, 2007 isl6540a typical application i (internal lin ear regulator with remote sense) isl6540a q1 q2 comp fb gnd vcc boot ugate lsoc lgate l in l out c hfin c bin c boot c hfout c bout r lsoc r 2 r fb c 1 c 2 c f1 d boot phase v out pgnd pvcc c f2 refin en ofs+ marctrl ofs- ss refout r ofs+ r ofs- c ss r fs fs vin r cc r hsoc c hsoc hsoc vsen- c pg_dly c 3 r 3 r os r 1 pg pg_dly v in internal 5.6v bias linear regulator vmon vsen+ c sen lindrv r marg vff vcc v sense- v sense+ 10 10 z in z fb c f3 c lsoc r boot gnd r vin c vff r vff
4 fn6288.3 may 29, 2007 typical application ii (external li near regulator without remote sense) isl6540a q1 q2 comp fb gnd vcc boot ugate lsoc lgate l in l out c hfin c bin c boot c hfout c bout r lsoc r 2 c 1 c 2 c f1 d boot phase v out pgnd pvcc c f2 refin refout ofs+ marctrl ofs- ss en r ofs+ r ofs- c ss r fs fs vin r cc r hsoc c hsoc hsoc vsen- c pg_dly c 3 r 3 r 1 pg pg_dly v in vmon vsen+ vcc r marg lindrv vff c f3 vcc z in z fb r os r vmonos r vmon1 c lc r lc r drv c lsoc r boot gnd r vin r vff c vff isl6540a
5 fn6288.3 may 29, 2007 typical application iii (d ual data rate i or ii) isl6540a q1 q2 comp fb gnd vcc boot ugate lsoc lgate l in l out c hfin c bin c boot c hfout c bout r lsoc r 2 r fb c 1 c 2 d boot phase v tt pgnd pvcc c f2 refin en ofs+ marctrl ofs- ss refout r ofs+ r ofs- c ss r fs fs vff r cc r hsoc c hsoc hsoc vsen- c pg_dly c 3 r 3 r 1 pg pg_dly 1.8v or 2.5v vmon vsen+ c sen lindrv r marg vin z fb z in c f4 vddq dimm 1k 5v c f1 0.9v (ddr ii) 0.9v (ddr i) 1.25v 15nf 1k r vff r en2 c lsoc gnd c vff r en1 isl6540a
6 fn6288.3 may 29, 2007 absolute maximum rati ngs thermal information input voltage, vin, vff, hsoc . . . . . . . . . . . . . . . . -0.3v to +22.0v driver bias voltage, pvcc . . . . . . . . . . . . . . . . . . . . -0.3v to +6.5v signal bias voltage, vcc . . . . . . . . . . . . . . . . . . . . . -0.3v to +6.5v boot voltage, v boot . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +36v boot to phase voltage (v boot- v phase ). . . . . -0.3v to 7v (dc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 9v (<10ns) phase voltage, v phase . . . . . . . . . v boot - 7v to v boot + 0.3v . . . . . . . . . . . . . . . . . . . . . .v boot - 9v (<10ns) to v boot + 0.3v ugate voltage . . . . . . . . . . . . . . . . v phase - 0.3v (dc) to v boot v phase - 5v (<20ns pulse width, 10 j) to v boot lgate voltage . . . . . . . . . . . . . . . gnd - 0.3v (dc) to vcc + 0.3v gnd - 2.5v (<20ns pulse width, 5 j) to vcc + 0.3v other input or output voltages . . . . . . . . . . . . . -0.3v to vcc +0.3v esd classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 2 recommended operating conditions input voltage, vin, vff . . . . . . . . . . . . . . . . . . . . 3.3v to 20v 10% driver bias voltage, pvcc . . . . . . . . . . . . . . . . . . . . . . 2.9v to 5.5v signal bias voltage, vcc . . . . . . . . . . . . . . . . . . . . . . . 2.9v to 5.5v boot to phase voltage (overcharged), v boot - v phase . . . . . .<6v ambient temperature range . . . . . . . . . . . . . . . . . . .-40c to +85c junction temperature range. . . . . . . . . . . . . . . . . .-40c to +125c thermal resistance (notes 1, 2) ja (c/w) jc (c/w) qfn package (notes 1, 2) . . . . . . . . 32 5 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . +150c maximum storage temperature range . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. ja is measured in free air with the component mounted on a high effe ctive thermal conductivity test board with ?direct attach? fe atures. 2. jc , "case temperature" location is at the center of the pa ckage underside exposed pad. see tech brief tb379 for details. electrical specifications recommended operating conditions, unless otherwise noted symbol parameter test conditions min typ max units input supply currents i vcc nominal vcc supply current vin = vcc = pvcc = 5v, fs = 600khz, ugate and lgate open -813ma i pvcc nominal pvcc supply current vin = vcc = pvcc = 5v; fs = 600khz, ugate and lgate open -3 4ma i vin nominal vin supply current vin = vcc = pvcc = 5v; fs = 600khz, ugate and lgate open -0.5 1ma i vcc_s shutdown vcc supply current en = 0v, vcc = pvcc = vin = 5v - 3 4 ma i pvcc_s shutdown pvcc supply current en = 0v, vcc = pvcc = vin = 5v - 1 2 ma i vin_s shutdown vin supply current en = 0v, vcc = pvcc = vin = 5v - 0.5 1 ma power-on reset por vcc_r rising vcc threshold 2.79 - 2.89 v por vcc_f falling vcc threshold 2.59 - 2.69 v por vcc_h vcc hysterisis 187 215 250 mv por pvcc_r rising pvcc threshold 2.79 - 2.91 v por pvcc_f falling pvcc threshold 2.59 - 2.70 v por pvcc_h pvcc hysterisis 193 215 250 mv por vff_r rising vff threshold 1.48 - 1.54 v por vff_f falling vff threshold 1.35 - 1.41 v por vff_h vff hysterisis 127 137 146 mv isl6540a
7 fn6288.3 may 29, 2007 enable v en_ref input reference voltage 0.485 0.500 0.515 v i en_hys hysteresis source current 7.5 10 11.5 a v en maximum input voltage - vcc + 0.3 - v oscillator osc fmax nominal maximum frequency gbd - 2000 - khz osc fmin nominal minimum frequency gbd - 250 - khz osc total variation fs = 250khz to 2mhz, vff = 3.3v to 20v -17 - +17 % v osc ramp amplitude - 0.16*vff - v p-p v osc_min ramp bottom -1.0 -v vff minimum usable vff voltage vcc = 5v - 3.3 - v pwm d max maximum duty cycle leading and trailing-edge modulation - 100 - % d min minimum duty cycle leading and trailing-edge modulation - 0 - % reference tracking v refin input voltage range vcc = 5v 0.068 - vcc - 1.8v v v refin_os external reference offset refin = 0.6v -1.8 0 2.2 mv i refout maximum drive current c l =1 f, vcc = 5v, refout = 1.25v - 19 - ma v refout output voltage range c l =1 f 0.01 - vcc - 1.8v v v refout_os maximum output voltage offset c l =1 f refout = 1.25v -6 - 11 mv c refout_min minimum load capacitance refout = 1.25v - 1.0 - f v refin_dis input disable voltage vcc = 5v vcc - 0.6 - vcc - 0.58 v reference v ref_com reference voltage t a = 0c to +70c 0.587 0.591 0.595 v v ref_ind t a = -40c to +85c 0.585 0.591 0.597 v v sys_com system accuracy t a = 0c to +70c -0.68 - 0.68 % v sys_ind t a = -40c to +85c -1.0 - 1.0 % error amplifier dc gain r l = 10k, c l = 100p, at comp pin - 88 - db ugbw unity gain-bandwidth r l = 10k, c l = 100p, at comp pin - 15 - mhz sr slew rate r l = 10k, c l = 100p, at comp pin - 6 - v/ s differential amplifier ug dc gain standard instrumentation amplifier - 0 - db ugbw unity gain bandwidth - 20 - mhz sr slew rate comp = 10pf - 10 - v/ s v offset_ind offset -1.9 0 1.9 mv i vsen- negative input source current - 6 - a input common mode range max - vcc - 1.8 - v input common mode range min - -0.2 - v v vsen_dis vsen- disable voltage - vcc - v electrical specifications recommended operating conditions, unless otherwise noted (continued) symbol parameter test conditions min typ max units isl6540a
8 fn6288.3 may 29, 2007 internal linear regulator i vin maximum current - 200 - ma r lin saturated equivalent impedance v in = 3.3v, load = 100ma - 2 3.9 pvcc linear regulator voltage v in = 22v, load = 0 to 100ma 5.42 5.50 5.71 v vin dv/dt_max maximum vin dv/dt v in = 0 v to v in step, pvcc < 2.0v at v in application; v in > 6.5v -1 -v/ s v in = 2.0 v to v in step, 2.0v < pvcc at v in application; v in > 6.5v -0.05 -v/ s external linear regulator lin_drv maximum sinking drive current 3.2 5 6.4 ma operational transconductance amplifier (ota) dc gain c ss =0.1 f, at ss pin - 88 - db drive capability c ss =0.1 f, at ss pin 30 37 44 a gate drivers r ugate ugate source resistance 500ma source current, pvcc = 5.0v - 1.0 - i ugate ugate source saturation current v ugate-phase = 2.5v, pvcc = 5.0v - 2.0 - a r ugate ugate sink resistance 500ma sink current, pvcc = 5.0v - 1.0 - i ugate ugate sink saturation current v ugate-phase = 2.5v, pvcc = 5.0v - 2.0 - a r lgate lgate source resistance 500ma source current, pvcc = 5.0v - 1.0 - i lgate lgate source saturation current v lgate = 2.5v, pvcc = 5.0v - 2.0 - a r lgate lgate sink resistance 500ma sink current, pvcc = 5.0v - 0.4 - i lgate lgate sink saturation current v lgate = 2.5v, pvcc = 5.0v - 4.0 - a overcurrent protection (ocp) i lsoc low side ocp (lsoc) current source lsoc = 0v to vcc - 1.0v, t a = 0c to +70c 86 100 107 a lsoc = 0v to vcc - 1.0v, t a = -40c to +85c 84 100 109 a i lsoc_ofset lsoc maximum offset error vcc = 2.9v and 5.6v t sample < 10 s - 2 - mv i hsoc high side ocp (hsoc) current source hsoc = 0.8v to 22v t a = 0c to +70c 91 100 106 a hsoc = 0.8v to 22v t a = -40c to +85c 89 100 107 a i hsoc_low hsoc = 0.3v to 0.8v 84 - 107 a i hsoc_ofset hsoc maximum offset error vcc = 2.9v and 5.5v t sample < 10 s - 2 - mv margining control v marg minimum margining voltage of internal reference r marg = 10k , r ofs- = 6.01k , mar_crtl = 0v -187 -197 -209 mv v marg maximum margining voltage of internal reference r marg = 10k , r ofs+ = 6.01k , mar_crtl = vcc 185 197 208 mv n marg margining transfer ratio n marg = (v ofs- -v ofs+ )/v marg 4.84 5 5.22 sdr mar_ctrl positive margining threshold 1.51 1.8 2.02 v mar_ctrl negative margining threshold 0.75 0.9 1.05 v mar_ctrl tri-state input level disable mode 1.21 1.325 1.40 v power good monitor v uvr undervoltage rising trip point -7% -9% -11% v ss v uvf undervoltage falling trip point -13% -15% -17% v ss v ovr overvoltage rising trip point 13% 15% 17% v ss electrical specifications recommended operating conditions, unless otherwise noted (continued) symbol parameter test conditions min typ max units isl6540a
9 fn6288.3 may 29, 2007 functional pin description vsen+ (pin 1) this pin provides differential remote sense for the isl6540a. it is the positive input of a st andard instrumentation amplifier topology with unity gain, and should connect to the positive rail of the load/processor. the voltage at this pin should be set equal to the internal system reference voltage (0.591v typical). vsen- (pin 2) this pin provides differential re mote sense for the regulator. it is the negative input of the instrumentation amplifier, and should connect to the negative rail of the load/processor. typically 6 a is sourced from this pin. the output of the remote sense buffer is disabled (high impedance) by pulling vsen- to vcc. refout (pin 3) this pin connects to the unmargined system reference through an internal buffer. it has a 19ma drive capability with an output common mode range of gnd to vcc. the refout buffer requires at least 1 f of capacitive loading to be stable. this pin should not be left floating. refin (pin 4) when the external reference pin (refin) is not within ~1.8v of vcc, the refin pin is used as the system reference instead of the inte rnal 0.591v reference. the recommended refin input voltage range is ~68mv to vcc - 1.8v. ss (pin 5) this pin provides soft-start functionality for the isl6540a. a capacitor connected to ground along with the internal 37a operational transconductance amplifier (ota), sets the soft-start interval of the converter. this pin is directly connected to the non-inverting input of the error amplifier. to prevent noise injection into the error amplifier the ss capacitor should be located next to the ss and gnd pins. ofs+ (pin 6) this pin sets the positive margining offset voltage. resistors should be connected to gnd (r ofs+ ) and ofs- (r marg ) from this pin. with mar_ctrl logic low, the internal 0.591v reference is developed at the ofs+ pin across resistor r ofs+ . the voltage on ofs+ is driven from ofs- through r marg . the resulting voltage differential between ofs+ and ofs- is divided by 5 and imposed on the system reference. the maximum designed offset of 1v between ofs+ and ofs- pins translates to a 200mv offset. ofs- (pin 7) this pin sets the negative margin ing offset voltage. resistors should be connected to gnd (r ofs- ) and ofs+ (r marg ) from this pin. with mar_ctrl logic low, the internal 0.591v reference is developed at the ofs- pin across resistor r ofs- . the voltage on ofs- is driven from ofs+ through r marg . the resulting voltage differential between ofs+ and ofs- is divided by 5 and imposed on the system reference. the maximum designed offset of -1v between ofs+ and ofs- pins translates to a -200mv offset of the system reference. vcc (pin 8, analog circuit bias) this pin provides power for the isl6540a analog circuitry. the pin should be connected to a 2.9v to 5.5v bias through an rc filter from pvcc to prev ent noise injection into the analog circuitry. this pin can be powered off the internal or external linear regulator options. marctrl (pin 9) the marctrl pin controls margining function, a logic high enables positive margining, a logic low sets negative margining, a high impedance disables margining. pg_dly (pin 10) provides the ability to de lay the output of the pgood assertion by connecting a capaci tor from this pin to gnd. a 0.1 f capacitor produces approximately a 7ms delay. pgood (pin 11) provides an open drain power good signal when the output is within 9% of nominal output regulation point with 6% v ovf overvoltage falling trip point 7% 9% 11% v ss t pg_dly pgood delay c pg_dly = 0.1 f-7.1-ms i pg_dly pgood delay source current 17 21 24 a v pg_dly pgood delay threshold voltage 1.45 1.49 1.52 v i pg_low pgood low output voltage i pgood = 5ma - - 0.150 v i pg_max maximum sinking current v pgood = 0.8v 23 - - ma v pg_max maximum open drain voltage vcc = 3.3v - 6 - v note: 3. test conditions identified as ?gbd ? are guaranteed by design simulation. electrical specifications recommended operating conditions, unless otherwise noted (continued) symbol parameter test conditions min typ max units isl6540a
10 fn6288.3 may 29, 2007 hysteresis (15%/9%), and after soft-start is complete. pgood monitors the vmon pin. en (pin 12) this pin is compared with an internal 0.50v reference and enables the soft-start cycle. th is pin also can be used for voltage monitoring. a 10 a current source to gnd is active while the part is disabled, and is inactive when the part is enabled. this provides functionality for programmable hysteresis when the en pin is used for voltage monitoring. vff (pin 13) the voltage at this pin is used for input voltage feed forward compensation and sets the internal oscillator ramp peak to peak amplitude at 0.16*vff. an external rc filter may be required at this pin in noi sy input environments. the minimum recommended vff voltage is 2.97v. vin (pin 14, internal linear regulator input) this pin should be tied directly to the input rail when using the internal or external linear regulator options. it provides power to the external/internal linear drive circuitry. when used with an external 3.3v to 5v supply, this pin should be tied directly to pvcc. lin_drv (pin 15, external linear regulator drive) this pin allows the use of an external pass element to power the ic for input voltages above 5.0v. it should be connected to gnd when using an external 5v supply or the internal linear regulator. when using the external linear regulator option, this pin should be co nnected to the gate of a pmos pass element, a pull-up resistor must be connected between the pmos device?s gate and source for proper operation. pvcc (pin 16, driver bias voltage) this pin is the output of the internal series linear regulator. it also provides the bias for both low side and high side mosfet drivers. the maximum voltage differential between pvcc and pgnd is 6v. its recommended operational voltage range is 2.9v to 5.5v. at minimum a 10 f capacitor is required for decoupling pvcc to pgnd. for proper operation the pvcc capacitor should be located next to the pvcc and the pgnd pins and s hould be connected to these pins with dedicated traces. lgate (pin 17) this pin provides the drive for the low side mosfet and should be connected to its gate. pgnd (pin 18, power ground) this pin connects to the low side mosfet's source and provides the ground return path for the lower mosfet driver and internal power circuitries. in addition, pgnd is the return path for the low side mosfet?s r ds(on) current sensing circuit. phase (pin 19) this pin connects to the source of the high side mosfet and the drain of the low side mosfet. this pin represents the return path for the high side gate driver. during normal switching, this pin is used for high side and low side current sensing. ugate (pin 20) this pin provides the drive for the high side mosfet and should be connected to its gate. boot (pin 21) this pin provides the bootstrap bias for the high side driver. the absolute maximum voltage differential between boot and phase is 6.0v (including the voltage added due to the overcharging of the bootstrap capacitor); its operational voltage range is 2.5v to 5.5v with respect to phase. it is recommended that a 2.2 resistor be placed in series with the bootstrap diode to prevent over charging of the boot capacitor during normal operation. hsoc (pin 22) the high side sourcing current limit is set by connecting this pin with a resistor and capacitor to the drain of the high side moseft. a 100 a current source develops a voltage across the resistor which is then compared with the voltage developed across the high side mosfet. an initial ~120ns blanking period is used to eliminate sampling error due to the switching noise before the current is measured. lsoc (pin 23) the low side source and sinking current limit is set by placing a resistor (r lsoc ) and capacitor between this pin and pgnd. a 100 a current source de velops a voltage across r lsoc which is then compared with the voltage developed across the low side mosfet when on. the sinking current limit is set at 1x of the nominal sourcing limit in isl6540a. an initial ~120ns blanking period is used to eliminate the sampling error due to switching noise before the current is measured. fs (pin 24) this pin provides oscillator switching frequency adjustment by placing a resistor (r fs ) from this pin to gnd. comp (pin 25) this pin is the error amplifier output. it should be connected to the fb pin through the desired compensation network. fb (pin 26) this pin is the inverting input of the error amplifier and has a maximum usable voltage of vcc - 1.8v. when using the internal differential remote sense functionality, this pin should be connected to vmon by a standard feedback network. in the event the remote sense buffer is disabled, the vmon pin should be connected to vout by a resistor divider along with fb?s compensation network. isl6540a
11 fn6288.3 may 29, 2007 gnd (pin 27, analog ground) signal ground for the ic. all voltage levels are measured with respect to this pin. this pin should not be left floating. vmon (pin 28) this pin is the output of t he differential remote sense instrumentation amplifier. it is connected internally to the ov/uv/pgood comparators. the vmon pin should be connected to the fb pin by a standard feedback network. in the event of the remote sense buffer is disabled, the vmon pin should be connected to vout by a resistor divider along with fb?s compensation networ k. an rc filter should be used if vmon is to be connect ed directly to fb instead of to vout through a separate resistor divider network. gnd (bottom side pad, analog ground) signal ground for the ic. all voltage levels are measured with respect to this pin. this pin should not be left floating. functional description initialization the isl6540a automatically initializes upon receipt of power without requiring any special sequencing of the input supplies. the power-on reset (por) function continually monitors the input supply voltages (pvcc, vff, vcc) and the voltage at the en pin. assuming the en pin is pulled to above ~0.50v, the por function initiates soft-start operation after all input supplies exceed their por thresholds. with all input supplies above their por thresholds, driving the en pin above 0.50v initiates a soft-start cycle. in addition to normal ttl logic, the enable pin can be used as a voltage monitor with programmable hysteresis through the use of the internal 10 a sink current and an external resistor divider. this feature is especially designed for applications that have input rails greater than a 3.3v and require a specific input rail por and hysteresis levels for better undervoltage protection. consider for a 12v application choosing r up =100k and r down =5.76k there by setting the rising threshold (v en_rth ) to ~10v and the falling threshold (v en_fth ) to ~9v, for 1v of hysteresis (v en_hys ). care should be taken to prevent the voltage at the en pin from exceeding vcc when using the programmable uvlo functionality. soft-start the por function activates the internal 37 a ota which begins charging the external capacitor (c ss ) on the ss pin to a target voltage of vcc. th e isl6540a?s soft-start logic continues to charge the ss pi n until the voltage on comp exceeds the bottom of the oscillator ramp, at which point, the driver outputs are enabled, with the low side mosfet first being held low for 200ns to provide for charging of the bootstrap capacitor. once the driver outputs are enabled, the ota?s target voltage is then changed to the margined (if margining is being used) reference voltage (v ref_marg ), and the ss pin is ramped up or down accordingly. this method reduces startup surge currents due to a pre-charged output by inhibiting regulator switching until the control loop enters its linear region. by ramping the positive input of the error amplifier to vcc and then to v ref_marg , it is even possible to mitigate surge currents from outputs that are pre-charged above the set output voltage. as the ss pin connects directly to the non-inverting input of the error amplifier, noise on this pin should be kept to a minimum through careful routing and part placement. to prevent noise injection into the error amplifier the ss capacitor should be located within 150 mils of the ss and gnd pins. soft-start is declared done when the drivers have been enabled and the ss pin is within 3mv of v ref_marg . vcc por pvcc por vff por en por soft-start high = above por; low = below por and figure 1. soft-start initialization logic v ref i en_hys =10 a r up r down vin r up v en_hys i en_hys ------------------------- - = r down r up v ? en_ref v en_fth v en_ref ? -------------------------------------------------------- - = v en_fth v en_rth v en_hys ? = sys_enable figure 2. enable por circuit figure 3. undervoltage-overvoltage window -15% -9% v ref_marg +9% +15% vmon uv uv ov good good t pg_dly c pg_dly 1.49v 21 a --------------- - ? = isl6540a
12 fn6288.3 may 29, 2007 power good the power good comparator references the voltage on the soft-start pin to prevent accid ental tripping during margining. the trip points are shown on figure 3. additionally, power good will not be asserted until after the completion of the soft-start cycle. a 0.1 f capacitor at the pg_dly pin will add an additional ~7ms delay to the assertion of power good. pg_dly does not delay the de-assertion of power good. under and overvoltage protection the undervoltage (uv) and overvoltage (ov) protection circuitry compares the voltage on the vmon pin with the reference that tracks with the ma rgining circuitry to prevent accidental tripping. uv and ov functionality is not enabled until the end of soft-start. an ov event is detected a synchronously and causes the high side mosfet to turn off, the low side mosfet to turn on (effectively a 0% duty cycle), and pgood to pull low. the regulator stays in this state and overrides sourcing and sinking ocp protections until the ov event is cleared. an uv event is detected asynchronously and results in the pgood pulling low. overcurrent protection the isl6540a monitors both the high side mosfet and low side mosfet for overcurrent events. dual sensing allows the isl6540a to detect overcurrent faults at the very low and very high duty cycles that can result from the isl6540a?s wide input range. the ocp function is en abled with the driv ers at startup and detects the peak current during each sensing period. a resistor and a capacitor between the lsoc pin and gnd set the low side source and sinking current limits. a 100 a current source develops a voltage across the resistor which is then compared with the voltage developed across the low side mosfet at conduction mode. the measurement comparator uses offset correcting circuitr y to provide precise current measurements with roughly 2mv of offset error. an ~120ns blanking period, implemented on the upper and lower mosfet current sensing circuitries, is used to reduce the current sampling error due to the leading-edge switching noise. an additional 120ns low pass filter is used to further reduce measurement error due to noise. in sourcing current applications, the lsoc voltage is inverted and compared with the voltage across the mosfet while on. when this voltage exceeds the lsoc set voltage, a sourcing ocp fault is triggered. a 1000pf or greater filter capacitor should be used in parallel with r lsoc to prevent on chip parasitics from impacting the accuracy of the ocp measurement. the isl6540a?s sinking current limit is set to the same voltage as its sourcing limit. in sinking applications, when the voltage across the mosfet is greater than the voltage developed across the resistor (r lsoc ) a sinking ocp event is triggered. to avoid non-synchronous operation at light load, the peak to peak output inductor ripple current should not be greater than twice of the sinking current limit. the high side sourcing current limit is set by connecting the hsoc pin with a resistor (r hsoc ) and a capacitor to the drain of the high side moseft. a 100 a current source develops a voltage across the resistor which is then compared with the voltage developed across the high side mosfet while on. when the voltage drop across the mosfet exceeds the voltage drop across the resistor, a sourcing ocp event occurs. a 1000pf or greater filter capacitor should be used in parallel with r hsoc to prevent on chip parasitics from impacting the accuracy of the ocp measurement and to smooth the voltage across r hsoc in the presence of switching noise on the input bus. sourcing ocp faults cause the r egulator to disable (ugate and lgate drives pulled low, pgood pulled low, soft-start capacitor discharged) itself for a fixed period of time after which a normal soft-start sequence is initiated. the period of time the regulator waits before attempting a soft-start sequence is set by three charge and discharge cycles of the soft-start capacitor. sinking ocp faults cause the low side mosfet drive to be disabled, effectively operating the isl6540a in a non-synchronous manner. the fault is maintained for three clock cycles at which point it is cleared and normal operation is restored. ovp fault implementation overrides sourcing r lsoc i oc_source i 2 ---- - + ?? ?? r ? ds on () ,l i lsoc n l ? -------------------------------------------------------------------------------------- = i = v in - v out f s l ------------------------------- - v out v in --------------- - ? i oc_sink i lsoc n l ? r lsoc ? r ds on () ,l ------------------------------------------------------- - i 2 ---- - ? = n l number of low side mosfets = r lsoc i oc_source r ? ds on () lowside 100 a --------------------------------------------------------------------------------------- = simple low side ocp equation detailed low side ocp equations (eq. 1) (eq. 1) (eq. 2) r hsoc i oc_source i 2 ---- - + ?? ?? r ? ds on () ,u i hsoc n u ? --------------------------------------------------------------------------------------- = n u number of high side mosfets = r hsoc i oc_source r ? ds on () highside 100 a ---------------------------------------------------------------------------------------- - = simple high side ocp equation detailed high side ocp equation (eq. 3) (eq. 4) isl6540a
13 fn6288.3 may 29, 2007 and sinking ocp events, immediately turning on the low side mosfet and turning off the high side mosfet. the oc trip point varies mainly due to the mosfets r ds(on) variations and system noise. to avoid overcurrent tripping in the normal operating load range, find the r hsoc and/or r lsoc resistor from the previous detailed equations with: 1. maximum r ds(on) at the highest junction temperature. 2. minimum i lsoc and/or i hsoc from specification table. 3. determine the overcurrent trip point greater than the maximum output continuous current at maximum inductor ripple current. frequency programming by tying a resistor to gnd from fs pin, the switching frequency can be set between 250khz and 2mhz. oscillator/vff the oscillator is a triangle waveform, providing for leading and falling edge modulation. the bottom of the oscillator waveform is set at 1.0v. the ramp's peak to peak amplitude is determined from the voltage on the vff (voltage feed forward) pin by the equation: vosc = 0.16*vff. an internal rc filter of 233k and 2pf (341khz) provides filtering of the vff voltage. an external rc filter may be required to augment this filter in the event th at it is insufficient to prevent noise injection or control loop interactions. voltages below 2.9v on the vff pin may result in undesirable operation due to extremely small peak to peak oscillator waveforms. the oscillator waveform should not exceed vcc -1.0v. for high vff voltages the internal/external 5.5v linear regulator should be used. 5.5v on vcc pr ovides sufficient headroom for 100% duty cycle operation when using the maximum vff voltage of 22v. in the event of sustained 100% duty cycle operation, defined as 32 clock cycles where no lg pulse is detected, lg will be pulsed on to refresh the design?s bootstrap capacitor. internal series linear regulator the vin pin is connected to pvcc with a 2 internal series linear regulator, which is internally compensated. the external series linear regulator option should be used for applications requiring pass elements of less than 2 . when using the internal regulator, the lin_drv pin should be connected directly to gnd. the pvcc and vin pins should have a bypasses capacitor (at least 10 f on pvcc is required) connected to pgnd. for proper operation the pvcc capacitor must be within 150 mils of the pvcc and the pgnd pins, and be connected to these pins with dedicated traces. the internal series linear regulator?s input (vin) can range between 3.3v to 20v 10%. the internal linear regulator is to provide power for both the internal mosfet drivers through the pvcc pin and the analog circuitry through the vcc pin. the vcc pin should be connected to the pvcc pin with an rc filter to prevent high frequency driver switching noise from entering the analog circuitry. when vin drops below 5.5v, the pass element will saturate; pvcc will track vin, minus the dropout of the linear regulator: pvcc = vin-2xi vin . when used with an external 5v supply, the vin pin should be tied directly to pvcc. at startup (pvcc = 0v and vin = 0v) the dv/dt on vin should be kept below 1v/ s to prevent electrical overstress on pvcc. care should be taken to keep the dv/dt on vin below 0.05v/ s if the initial steady state voltage on pvcc is above 2.0v, as electrical ov erstress on pvcc is otherwise possible. external series linear regulator the lin_drv pin provides sinking drive capability for an external pass element linear regulator controller. the external linear options are especially useful when the internal linear dropout is too large for a given application. when using the external linear regulator option, the lin_drv pin should be connected to the gate of a pmos device, and a resistor should be connected between its gate and source. a resistor and a capacitor should be connected from gate to source to compensate the control loop. a pnp device can be used instead of a pmos device in which case the lin_drv pin should be conn ected to the base of the pnp pass element. the sinking capability of the lin_drv pin is 5ma, and should not be exceeded if using an external resistor for a pmos device. the designer should take care in designing a stable system when using external pass elements. the vcc pin should be connected to the pvcc pin with an rc filter to prevent high frequency driver switching noise from entering the analog circuitry. high speed mosfet gate driver the integrated driver has similar drive capability and features to intersil's isl6605 stand alone gate driver. the pwm tri-state feature helps pr event a negative transient on the output voltage when the outpu t is being shut down. this eliminates the schottky diode th at is used in some systems 10 200k 1m 5 40 80 30 20 2m 400k 600k 800k 300k 7 60 figure 4. r fs resistance vs frequency frequency (hz) resistance (k ) fs hz [] 1.178 10 10 r t [] 0.973 ? (r t to gnd) ? (eq. 5) isl6540a
14 fn6288.3 may 29, 2007 for protecting the microprocessor from reversed-output- voltage damage. see the isl6605 datasheet for specification parameters that are not defined in the current isl6540a ?electrical specifications? table on page 6. a 1-2 resistor is recommended to be in series with the bootstrap diode when using vccs above 5.0v to prevent the bootstrap capacitor from over charging due to the negative swing of the trailing edge of the phase node. margining control when the mar_ctrl is pulled high or low, the positive or negative margining functionalit y is respectively enabled. when mar_ctrl is left floating, the function is disabled. upon up margining, an internal buffer drives the ofs- pin from vcc to maintain ofs+ at 0.591v. the resistor divider, r marg and r ofs+ , causes the voltage at ofs- to be increased. similarly, upon down margining, an internal buffer drives the ofs+ pin from vcc to maintain ofs- at 0.591v. the resistor divider, r marg and r ofs- , causes the voltage at ofs+ to be increased. in both modes the voltage difference between ofs+ and ofs- is then sensed with an instrumentation amplifier and is converted to the desired margining voltage by a 5:1 ratio. the maximum designed margining range of the isl6540a is 200mv, this sets the minimum value of r ofs+ or r ofs- at approximately 5.9k for an r marg of 10k for a maximum of 1v across r marg . the ofs pins are completely independent and can be set to different margining levels. the maximum usable reference voltage for the isl6540a is vcc-1.8v, and should not be exceeded when using the margining functionality, i.e, v ref_marg 15 fn6288.3 may 29, 2007 as some applications will not use the differential remote sense, the output of the remote sense buffer can be disabled (high impedance) by pulling vsen - within 1.8v of vcc. as the vmon pin is connected internally to the ov/uv/pgood comparator, an external resistor divider must then be connected to vmon to provide correct voltage information for the ov/uv comparator. an rc filter should be used if vmon is to be connected directly to fb instead of to vout through a separate resistor divider network. this filter prevents noise injection from disturbing the ov/uv/pgood comparators on vmon. vmon may also be connected to the ss pin, which completely bypasses the ov/uv/pgood functionality. application guidelines layout considerations mosfets switch very fast and efficiently. the speed with which the current transitions from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. these voltage spikes can degrade efficiency, radiate noise into the circuit and lead to device over-voltage stress. careful component layout and printed circuit design minimizes the voltage spikes in the converter. consider, as an example, the turnoff transition of the upper pwm mosfet. prior to turnoff, the upper mosfet is carrying the output inductor current. during the turnoff, current stops flowing in the upper mosfet and is picked up by the lower mosfet. any inductance in the switched current path generates a large voltage spike during the switching interval. careful component selection, tight layout of the critical components, and short, wide circuit traces minimize the magnitude of voltage spikes. there are two sets of critical components in a dc-dc converter using a isl6540a controller. the power components are the most critical because they switch large currents and have the potential to create large voltage spikes, as well as induce noise into sensitive, high impedance adjacent nodes. next are small signal components that connect to sensitive nodes or supply critical bypassing current and signal coupling. equally important are the conne ctions of the internal gate drives (ugate, lgate, phase, pgnd, boot): since they drive the power train mosfets using short, high current pulses, it is important to size them accordingly and reduce their overall impedance. whil e not always esthetically pleasing, straightest connecti ons encircling the least area result in the lowest parasitic inductance build-up, and, consequentially, are the better choice. the power train components should be placed first. locate the input capacitors close to the power switches. minimize the length of the connections between the input capacitors, c in , especially the high frequency decoupling, and the power switches. locate the ou tput inductor and output capacitors between the mosfets and the load. locate all the high-frequency decoupling capacitors (ceramics) as close as practicable to their decoupling target, making use of the shortest connection paths to any internal planes, such as vias to gnd immediately next, or even onto the capacitor?s grounded solder pad. the critical small signal components include the bypass capacitors for vin, vcc a nd pvcc. locate the bypass capacitors, c bp , close to the device. it is especially important to locate the components associated with the feedback circuit close to their respective controller pins, since they belong to a high-impedance circuit loop, sensitive vsen- vsen+ comp fb vmon r fb r os z in z fb ov/uv error amp comp c sen 1.8v vcc v ss 10 10 vout (local) gnd (local) vsense+ gain=1 vsense- figure 6. simplified unity gain differenital sensing implementation (remote) (remote) isl6540a
16 fn6288.3 may 29, 2007 to emi pick-up. place all t he other highlighted components close to the respective pins of the isl6540a. a multi-layer printed circuit board is recommended. figure 7 shows the connections of the critical components of the converter. note that capacitors c xxin and c xxout could each represent numerous physical capa citors. dedica te one solid layer, usually the one underneath the component side of the board, to a ground plane and make all critical component ground connections with vias to this layer. dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. keep the phase island as small as practicable, while st ill allowing for proper heatsinking of the lower mosfet. the power plane should support the input power and output power nodes. use copper filled polygons on the top and bottom circuit layers for large current- carrying circuit nodes. use the remaining printed circuit layers for small signal wiring. size the trace interconnects commensurate with the signals they are carrying. use narrow (0.004? to 0.008?) and short traces for the high-impedance, small-signal connections, such as the feedback, compensation, soft-start, frequency set, reference input, offset, etc. th e wiring traces from the ic to the mosfets? gates and sources should be wide (0.02? to 0.05?) and short, encircling th e smallest area possible. the metal pad of the isl6540a?s package should be connected to the ground plane via 6-9 small vias evenly placed in the bottom pad?s footprint. the gnd and pgnd pins should be connected to this bottom pad to find a convenient, low inductance path to the rest of the circuitry. this recommended connection provides not only an electrically low impedance path, but a low thermal path as well, helping with the heat dissipation taking place in the part. via connection to ground plane island on/power plane layer island on circuit plane layer key locate close to ic figure 7. printed circuit board power planes and islands locate near load (minimize connection path) (c hfin ) c bin (c hfout ) c bout r 1 c 1 heavy trace on circuit plane layer locate near switching transistors (minimize connection path) (minimize connection path) r fb r os isl6540a q1 q2 comp fb gnd vcc boot ugate lsoc lgate l in l out c boot r lsoc r 2 c 2 (c f1 ) d boot phase v out pvcc (c f2 ) refin en ofs+ marctrl ofs- ss refout r ofs+ r ofs- c ss r fs fs vin r cc r hsoc c hsoc hsoc vsen- c pg_dly c 3 r 3 pg pg_dly +3.3v to +20v internal bias linear regulator vmon vsen+ c sen lindrv r marg vff vcc v sense- v sense+ (c f3 ) c lsoc r boot pgnd r vin c vff r vff r ls- r ls+ isl6540a
17 fn6288.3 may 29, 2007 compensating the converter the isl6540a single-phase converter is a voltage-mode controller. this section highlight s the design considerations for a voltage-mode controller requiring external compensation. to address a broad range of applications, a type-3 feedback network is recommended (see figure 8). figure 9 highlights the voltage-mode control loop for a synchronous-rectified buck converter, when using an internal differential remote sense amplifier. the output voltage (v out ) is regulated to the reference voltage, vref, level. the error amplifier output (comp pin voltage) is compared with the oscillator (osc) triangle wave to provide a pulse-width modulated wave with an amplitude of v in at the phase node. the pwm wave is smoothed by the output filter (l and c). the output filter capacitor bank?s equivalent series resistance is represented by the series resistor esr. the modulator transfer function is the small-signal transfer function of v out /v comp . this function is dominated by a dc gain, given by d max v in /v osc , and shaped by the output filter, with a double pole break frequency at f lc and a zero at f ce . for the purpose of this analysis c and esr represent the total output capacitance and its equivalent series resistance. the compensation network consis ts of the error amplifier (internal to the isl6540a) and the external r 1 -r 3 , c 1 -c 3 components. the goal of the compensation network is to provide a closed loop transfer f unction with high 0db crossing frequency (f 0 ; typically 0.1 to 0.3 of f sw ) and adequate phase margin (better than 45). phase margin is the difference between the closed loop phase at f 0db and 180. the equations that follow relate the compensation network?s poles, zeros and gain to the components (r 1 , r 2 , r 3 , c 1 , c 2 , and c 3 ) in figures 8 and 9. use the following guidelines for locating the poles and zeros of the compensation network: 1. select a value for r 1 (1k to 10k , typically). calculate value for r 2 for desired converter bandwidth (f 0 ). if setting the output voltage to be equal to the reference set voltage as shown in figure 8, the design procedure can be followed as presented. however, when setting the output voltage via a resistor divider placed at the input of the differential amplifier (as shown in figure 9), in order to compensate for the attenuation introduced by the resistor divider, the below obtained r 2 value needs be multiplied by a factor of (r os +r fb )/r os . the remainder of the calculations remain unchanged, as long as the compensated r 2 value is used. a small capacitor, c sen in figure 9, can be added to filter out noise, typically c sen is chosen so the corresponding time constant does not reduc e the overall phase margin of the design, typically this is 2x to 10x switching frequency of the regulator. as the isl6540a supports 100% duty cycle, d max equals 1. the isl6540a also uses feedforward com pensation, as such v osc is equal to 0.16 multiplied by the voltage at the vff pin. when tieing vff to v in , the equation 9 simplifies to: 2. calculate c 1 such that f z1 is placed at a fraction of the f lc , at 0.1 to 0.75 of f lc (to adjust, change the 0.5 factor to desired number). the higher t he quality factor of the output figure 8. compensation configuration for isl6540a when using differential remot e sense isl6540a comp c 1 r 2 r 1 fb vmon c 2 r 3 c 3 figure 9. voltage-mode buck converter compensation design - + e/a vref comp c 1 r 2 r 1 fb c 2 r 3 c 3 l c v in pwm circuit half-bridge drive oscillator esr external circuit isl6540a v out v osc dcr ugate phase lgate - + vmon vsen+ vsen- c sen r os r fb f lc 1 2 lc ? ? --------------------------- = f ce 1 2 c esr ?? --------------------------------- = (eq. 8) r 2 v osc r 1 f 0 ?? d max v in f lc ?? --------------------------------------------- = (eq. 9) r 2 0.16 r 1 f 0 ?? f lc ---------------------------------- = (eq. 10) isl6540a
18 fn6288.3 may 29, 2007 filter and/or the higher the ratio f ce /f lc , the lower the f z1 frequency (to maximize phase boost at f lc ). 3. calculate c 2 such that f p1 is placed at f ce . 4. calculate r 3 such that f z2 is placed at f lc . calculate c 3 such that f p2 is placed below f sw (typically, 0.5 to 1.0 times f sw ). f sw represents the regulator?s switching frequency. change the numerical factor to reflect desired placement of this pole. placement of f p2 lower in frequency helps reduce the gain of the compensation network at high frequency, in turn reducing the hf ripple component at the comp pin and minimizing resultant duty cycle jitter. it is recommended that a mathemat ical model is used to plot the loop response. check the loop gain against the error amplifier?s open-loop gain. verify phase margin results and adjust as necessary. the following equations describe the frequency response of the modulator (g mod ), feedback compensation (g fb ) and closed-loop response (g cl ): as before when tieing vff to vin terms in the above equations can be simplified as follows: compensation break frequency equations figure 10 shows an asymptotic plot of the dc/dc converter?s gain vs. frequency. the actual modulator gain has a high gain peak dependent on the quality factor (q) of the output filter, which is not shown. using the above guidelines should yield a compensation gain similar to the curve plotted. the open loop error amplifier gain bounds the compensation gain. check the compensation gain at f p2 against the capabilities of the error amplifier. the closed loop gain, g cl , is constructed on the log-log graph of figure 10 by adding the modulator gain, g mod (in db), to the feedback compensation gain, g fb (in db). this is equivalent to mu ltiplying the modulator transfer function and the compensation transfer function and then plotting the resulting gain. a stable control loop has a gain crossing with close to a -20db/decade slope and a phase margin greater than 45. include worst case component variations when determining phase margin. the mathematical model presented makes a number of approximations and is generally not accurate at frequencies approaching or e xceeding half the switching frequency. when designing compensation networks, select target crossover frequencies in the range of 10% to 30% of the switching frequency, f sw . component selection guidelines output capacitor selection an output capacitor is required to filter the output and supply the load transient current. t he filtering requirements are a function of the switching fr equency and the ripple current. the load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. these requirements are generally met with a mix of capacitors and careful layout. modern microprocessors produc e transient load rates above 1a/ns. high frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. the bulk filter capacitor values are generally determined by the esr (effective series resistance) and voltage rating requirements rather than actual capacitance requirements. high frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance c 1 1 2 r 2 0.5 f lc ?? ? ---------------------------------------------- - = (eq. 11) c 2 c 1 2 r 2 c 1 f ce 1 ? ??? -------------------------------------------------------- = (eq. 12) r 3 r 1 f sw f lc ------------ 1 ? --------------------- - = c 3 1 2 r 3 0.7 f sw ?? ? ------------------------------------------------ - = (eq. 13) g mod f () d max v in ? v osc ------------------------------ - 1sf () esr c ?? + 1sf () esr dcr + () c ?? s 2 f () lc ?? ++ ----------------------------------------------------------------------------------------------------------- ? = g fb f () 1sf () r 2 c 1 ?? + sf () r 1 c 1 c 2 + () ?? ---------------------------------------------------- ? = 1sf () r 1 r 3 + () c 3 ?? + 1sf () r 3 c 3 ?? + () 1sf () r 2 c 1 c 2 ? c 1 c 2 + -------------------- - ?? ?? ?? ?? + ?? ?? ?? ? ------------------------------------------------------------------------------------------------------------------------- g cl f () g mod f () g fb f () ? = where s f () , 2 fj ?? = (eq. 14) d max v in ? v osc ------------------------------ - 1v in ? 0.16 v in ? -------------------------- - 6.25 == (eq. 15) f z1 1 2 r 2 c 1 ?? ------------------------------ - = f z2 1 2 r 1 r 3 + () c 3 ?? ------------------------------------------------- = f p1 1 2 r 2 c 1 c 2 ? c 1 c 2 + -------------------- - ?? -------------------------------------------- - = f p2 1 2 r 3 c 3 ?? ------------------------------ - = (eq. 16) 0 f p1 f z2 open loop e/a gain f z1 f p2 f lc f ce compensation gain gain frequency modulator gain figure 10. asymptotic bode plot of converter gain closed loop gain 20 d max v ? in v osc ---------------------------------- - log 20 r2 r1 ------- - ?? ?? log log log f 0 g mod g fb g cl isl6540a
19 fn6288.3 may 29, 2007 components. consult with the manufacturer of the load on specific decoupling requirem ents. for example, intel recommends that the high frequency decoupling for the pentium pro be composed of at least forty (40) 1.0 f ceramic capacitors in the 1206 surface-mount package. follow on specifications have only increased the number and quality of required ceramic decoupling capacitors. use only specialized low-esr capacitors intended for switching-regulator applications for the bulk capacitors. the bulk capacitor?s esr will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. an aluminum electrolytic capacitor's esr value is related to the case size with lower esr avai lable in larger case sizes. however, the equivalent series inductance (esl) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. unfortunately, esl is not a specified parameter. work with your capacitor supplier and measure the capacitor?s impedance with fr equency to select a suitable component. in most case s, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. output inductor selection the output inductor is selected to meet the output voltage ripple requirements and minimize the converter?s response time to the load transient. the inductor value determines the converter?s ripple current and t he ripple voltage is a function of the ripple current. the ripple voltage and current are approximated by the following equations: increasing the value of inductance reduces the ripple current and voltage. however, the large inductance values reduce the converter?s response time to a load transient. one of the parameters limiting the converter?s response to a load transient is the time required to change the inductor current. given a sufficiently fast control loop design, the isl6540a will provide either 0% or 100% duty cycle in response to a load transient. the response time is the time required to slew the inductor current from an initial current value to the transient current le vel. during this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor. minimizing the response time can minimize the output capacitance required. the response time to a transient is different for the application of load and the removal of load. the following equations give the approximate response time interval for application and removal of a transient load: where: i tran is the transient load current step, t rise is the response time to the application of load, and t fall is the response time to the removal of load. with a lower input source such as 1.8v or 3.3v, the worst case response time can be either at the applicat ion or removal of load and dependent upon the output voltage setting. be sure to check both of these equations at the minimum and maximum output levels for the worst case response time. input capacitor selection use a mix of input bypass capacitors to control the voltage overshoot across the mosfets. use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time q1 turns on. place the small ceramic capacitors physically close to the mosfets and between the drain of q1 and the source of q2. the important parameters for the bulk input capacitor are the voltage rating and the rms current rating. for reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest rms current required by the circuit. the capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. the rm s current rating requirement for the input capacitor of a buck regulator is approximated in equation 19. for a through hole design, several electrolytic capacitors (panasonic hfq series or nichicon pl series or sanyo mv-gx or equivalent) may be needed. for surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. these capacitors must be capable of handling the surge-current at power-up. figure 11 provides an easy graphical approximation of the input rms requirements for a single-phase buck converter. i = v in - v out f s x l ------------------------------- - v out v in --------------- - ? v out = iesr (eq. 17) t fall l o i tran v out ------------------------------ - = t rise l o i tran v in v out ? ------------------------------- - = (eq. 18) i in rms , i o 2 dd 2 ? () i 2 12 -------- d + = d v o vin ---------- = or i inrms k icm i o ? = (eq. 19) isl6540a
20 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6288.3 may 29, 2007 mosfet selection/considerations the isl6540a requires 2 n-channel power mosfets. these should be selected based upon r ds(on) , gate supply requirements, and thermal management requirements. in high-current applications, the mosfet power dissipation, package selection and heatsink are the dominant design factors. the power dissi pation includes two loss components; conduction loss and switching loss. the conduction losses are the largest component of power dissipation for both the upper and the lower mosfets. these losses are distributed between the two mosfets according to duty factor (see the equations below). the upper mosfet exhibits turn-on and turn-off switching losses as well as the reve rse recover loss, while the synchronous rectifier exhibits body-diode conduction losses during the leading and trailing edge dead times. where d is the duty cycle = v o /vin; q rr is the reverse recover charge; t dl and t dt are leading and trailing edge dead time, and t on and t off are the switching intervals. these equations do not include the gate-charge losses that are proportional to the total gate charge and the switching frequency and partially dissipated by the internal gate resistance of the mosfets. ensure that both mosfets are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. a separate heatsink may be necessary depending upon mosfet power, package type, ambient temperature and air flow. 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 k icm duty cycle (d) figure 11. input-capacitor current multiplier for single-phase buck converter i lout = 0.25 x i out i lout = 0.5 x i out i lout = 0 p lower i o 2 i 2 12 -------- + ?? ?? r ds on () ,l n l --------------------------- ? 1d ? () p dead + ? = p dead i o i 12 ------ + ?? ?? v dt ? t dt ? i o i 12 ------ ? ?? ?? v dl ? t dl ? + f s ? = p sw i o i 12 ------ + ?? ?? t off ? i o i 12 ------ ? ?? ?? t on ? + vin f ? s ? = p upper i o 2 i 2 12 -------- + ?? ?? r ds on () ,u n u --------------------------- - ? dp sw p qrr ++ ? = p qrr q rr vin f ? s ? = (eq. 20) isl6540a
21 fn6288.3 may 29, 2007 isl6540a quad flat no-lead plastic package (qfn) micro lead frame pl astic package (mlfp) index d1/2 d1 d/2 d e1/2 e/2 e a 2x 0.15 b c 0.10 b a mc a n seating plane n 6 3 2 2 3 e 1 1 0.08 for odd terminal/side for even terminal/side c c section "c-c" nx b a1 c 2x c 0.15 0.15 2x b 0 ref. (nd-1)xe (ne-1)xe ref. 5 a1 4x p a c c 4x p b 2x a c 0.15 a2 a3 d2 d2 e2 e2/2 terminal tip side view top view 7 bottom view 7 5 c l c l e e e1 2 nx k nx b 8 nx l 8 8 9 area 9 4x 0.10 c / / 9 (datum b) (datum a) area index 6 area n 9 corner option 4x l1 l 10 l1 l 10 l28.5x5 28 lead quad flat no-lead plastic package (compliant to jedec mo-220vhhd-1 issue i) symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - 0.02 0.05 - a2 - 0.65 1.00 9 a3 0.20 ref 9 b 0.18 0.25 0.30 5,8 d 5.00 bsc - d1 4.75 bsc 9 d2 2.95 3.10 3.25 7,8 e 5.00 bsc - e1 4.75 bsc 9 e2 2.95 3.10 3.25 7,8 e 0.50 bsc - k0.20 - - - l 0.50 0.60 0.75 8 n282 nd 7 3 ne 7 3 p- -0.609 --129 rev. 1 11/04 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in millim eters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. features and dimensions a2, a3, d1, e1, p & are present when anvil singulation method is used and not present for saw singulation.

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